A design for test perspective on memory synthesis

A novel approach based on a branch and bound technique is presented for transformation of logical memories to map-pable physical memories while speciied parameters such as area, delay, memory test time and test strategy are satis-ed. The proposed algorithm uses the new test parameters to realize a logical memory with a set of physical memories which could be tested within the speciied test time using the speciied memory test strategy. The proposed framework generates and stores the realized logical memory in structural VHDL.